1. Field of the Invention
The present invention relates to a manufacturing method for a semiconductor package, and particularly to a manufacturing method for a semiconductor package for use in a flip chip.
2. Description of the Related Art
As shown in FIG. 1, a semiconductor package for use in a flip chip according to the prior art is made up of, for example, semiconductor chip 1 (also referred to as a "pellet"), case 3 having a depression which is a mounting portion for mounting semiconductor chip 1, and a cap 4 which seals the opening of the depression in case 3 and which further is affixed to semiconductor chip 1 and serves as a heat sink (heat discharge part). In addition, external terminal 8 for exchanging signals with semiconductor chip 1 is provided on the outer surface of case 3, and inner leads (internal wiring) 7 which are in electrical contact with external terminal 8 are arranged on the bottom surface of the depression of case 3.
In manufacturing such a semiconductor package, first, as shown in FIG. 2A, ball bumps 2 are attached to wiring connection terminals (also called "pads") (not shown in the figure) on the surface of semiconductor chip 1. Next, as shown in FIG. 2B, face bonding is effected between ball bumps 2 of semiconductor chip 1 and inner leads 7 on the bottom surface of the depression of case 3. Then, as shown in FIG. 2C, cap 4 is then bonded by means of resin 6 to semiconductor chip 1, which is mounted on case 3, and the opening of the depression of case 3 is sealed by cap 4 using resin 6.
However, in the manufacturing method of a semiconductor package of the prior art as shown in FIG. 2A-2C, when attaching cap 4, which also serves as a heat sink, after semiconductor chip 1 having attached ball bumps has already been mounted in case 3, the pressure at the time of sealing must be controlled both between cap 4 that doubles as a heat sink and the obverse surface of semiconductor chip 1 as well as between ball bumps 2 and inner leads 7 of case 3, and this control has been difficult. As a consequence, problems have occurred including incomplete sealing and cracking of semiconductor chips due to insufficient or excessive pressure at the time of sealing.